1. Field of the Invention
The present invention relates to a technology test circuit, a semiconductor integrated circuit, and a method and apparatus for supporting design of a circuit.
2. Description of the Related Art
Conventionally, before shipment of a semiconductor integrated circuit, a test is performed to check whether the circuit operates correctly. The test generally includes the following:
(1) A function test for checking basic functional operation of the semiconductor integrated circuit.
(2) A logic test for detecting a failure at a transistor level in the semiconductor integrated circuit.
(3) A delay test for checking whether the semiconductor integrated circuit operates at a target frequency.
Along with miniaturization of technology, fluctuations in delay are increased due to variations in the process, reduction of a power supply voltage, and cross talks. Since such delay fluctuations cannot be estimated qualitatively at the time of design, the delay fluctuations are handled as uncertain delay. Therefore, a margin for the delay should be provided at the time of design.
Increase of the margin makes a timing design difficult. Therefore, a delay calculation technique using a statistical technique is increasingly employed to eliminate an unnecessary delay margin.
However, if the delay margin is reduced, all the manufactured circuits may not operate at a target frequency. As a technique that screens such a timing failure circuit, an at-speed test must be performed, which performs a delay test at the timing of an actual device frequency. A technology for the at-speed test with a dedicated built-in circuit is disclosed in, for example, Japanese Patent Application Laid-Open Publication No. 2001-319500.
However, since the at-speed test is performed under a special condition called a test mode, which is different condition from a normal chip operating condition, the operation in the actual device is not necessarily assured even when it is successful in the at-speed test.
On the contrary, a chip normally operating in the actual device may not pass the at-speed test. The at-speed test is time-consuming. Moreover, the at-speed test requires a dedicated circuit called built-in-self-test (BIST) and an expensive device specially prepared for the at-speed test. Therefore, manufacturing cost increases.